Ex Parte Sato - Page 6

                Appeal 2007-1275                                                                              
                Application 09/824,248                                                                        

                      number are written in a header of the motion image file.  (Col. 10,                     
                      ll. 51-61.)    Figure 5 shows "exemplary qualities associated with                      
                      typical parameters of a reproduce [sic] system."  (Col. 4, ll. 22-23).  In              
                      particular, Figure 5 shows two different frame rate parameters -- i.e.,                 
                      30 frames per second and 15 frames per second.  (Fig. 5.)                               

                 7. In the camera of Shioji, a desired motion image signal is selected by a                   
                      selector (col. 3, ll. 49-50, 61-62), and the frame rate of the desired                  
                      motion image signal is detected by a detector (col. 3, ll. 50-51, 62-63;                
                      col. 4, ll. 3-4).  The desired motion image signal is reproduced by a                   
                      reproducer at the frame rate detected by the detector (col. 3, ll. 51-53,               
                      63-67).                                                                                 

                 8. Figure 1 of Shioji shows an embodiment of a digital camera that                           
                      includes:  a record/reproduce mode (R/P) select switch 20 and a                         
                      reproduce mode select switch 22; a system controller 26 connected to                    
                      switches 20 and 22; a CPU 19 connected to the system controller 26; a                   
                      video encoder 9 connected to a monitor 10 mounted on the camera                         
                      body; a memory control circuit 7 connected to a data storage area of                    
                      SDRAM 6; a disk control circuit 12 connected to a magneto-optical                       
                      disk 14; and a bus 8 connected to the CPU 19, memory control circuit                    
                      7, video encoder 9, and disk control circuit 12.  (Col 5, l. 22 to col. 7,              
                      l. 51.)                                                                                 




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