Appeal 2007-1360
Application 10/605,699
the farther a latch-up structure is from the current injection point the fewer
the carriers that will be available for structure latch-up, the invention
provides for greater contact periodicity in areas of the integrated circuit
remote from the injection source. (Specification, paragraphs [0021] and
[0041].
We affirm.
Claim 1 is illustrative of the invention and it reads as follows:
1. A CMOS semiconductor substrate comprising:
a substrate;
a plurality of circuit structures formed upon said substrate, wherein at
least one of said circuit structures has a susceptibility to a latch-up condition;
an injection site associated with said CMOS semiconductor structure;
and
a plurality of contact regions inter-spaced a varying distance between
said circuit structures.
The Examiner relies on the following prior art references to show
unpatentability:
Magee US 4,642,667 Feb. 10, 1987
Kim US 5,675,170 Oct. 7, 1997
Claims 1-10 and 15-31 stand rejected under 35 U.S.C. § 102(b) as
being anticipated by Kim. Claims 1, 7, and 11-14 stand rejected under 35
U.S.C. § 102(b) as being anticipated by Magee.
Rather than reiterate the arguments of Appellants and the Examiner,
reference is made to the Briefs and Answer for the respective details. Only
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