Appeal 2007-1540
Application 10/280,788
INVENTION
The invention is directed to an input buffer which protects an
integrated circuit from overvoltage conditions. See page 2 of Appellants’
Specification. Claim 17 is representative of the invention and reproduced
below:
17. A high speed input buffer electrically connected to an input
voltage pad, the high speed input buffer comprising:
a native transistor having a first contact electrically connected
to the input voltage pad,
a single ended input circuit electrically connected to a second
contact of the native transistor, and
a leakage element having a first electrical connection and a
second electrical connection, the first electrical connection of the
leakage element directly connected to the second contact of the first
native transistor and the second electrical connection of the leakage
element electrically connected to a VSS line, where the leakage
element is one of a single NMOS transistor where a gate contact of the
NMOS transistor is electrically connected only to the second contact
of the native transistor, and a resistor.
REFERENCES
The references relied upon by the Examiner are:
Nakakura US 5,512,844 Apr. 30, 1996
Metzler US 6,420,757 B1 Jul. 16, 2002
Cress US 6,483,386 B1 Nov. 19, 2002
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Last modified: September 9, 2013