Appeal 2007-1540
Application 10/280,788
REJECTIONS
Claims 17, 18, and 20 stand rejected under 35 U.S.C. § 103(a) as
unpatentable over Nakakura in view of Cress.
Claim 21 stands rejected under 35 U.S.C. § 103(a) as unpatentable
over Nakakura in view of Cress and Metzler.
Appellants contend that the Examiner’s rejections under 35 U.S.C. §
103(a) are in error. Appellants assert that Nakakura does not teach using a
native transistor and that while Cress teaches a native transistor, the clamp
circuit of Cress comprises two transistors rather than a leakage circuit with a
resistor or single transistor as claimed. Brief, p. 4.
We are not persuaded by Appellants' arguments. Each of independent
claims 17, 20, and 21 recites a circuit with a native transistor connected to an
input pad and a single end input circuit. Each of the independent claims also
recites a leakage element “directly connected to the second contact of the
first native transistor and the second electrical connection of the leakage
element electrically connected to a VSS line,” where the leakage element is
“a single NMOS transistor where a gate contact of the NMOS transistor is
electrically connected only to the second contact of the native transistor.”1
Cress teaches a circuit using a native transistor to provide high voltage
protection for a single ended input circuit. Abstract and col. 2, ll. 47-52.
The native transistor provides protection when a low voltage circuit is
connected to another circuit that operates at a higher voltage. Col. 1, ll. 15-
19. The native transistor M3 is connected between an input signal line and
1 Claims 17 and 20 recite that the leakage element alternatively is a resistor.
3
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