Appeal 2007-1552
Application 09/852,123
Rejection of claims 2-5 under 35 U.S.C. § 103(a) as unpatentable over Avery and
Smith
In rejecting claim 2, the Examiner found that “the use of a deeper doped
region or well to significantly increase the path length that avalanche generated
charge carriers have to travel as a means to increase the collector-to-emitter voltage
in bipolar transistor dynamics is a method well known in the art, as witnessed by
Smith” (Answer 4). Further, the Examiner held that it would have been obvious to
modify the ESD structure of Avery to include a deeper doped region or well to
significantly increase the path length charge carriers have to travel as illustrated in
Smith (Answer 5).
Appellants contend that “Smith has nothing to do with ESD protective
devices” and although “Smith illustrates a block labeled ESD circuit 15, Smith
clearly states that this ESD circuit 15 is not disclosed within the specification or
figures of the patent” (Reply Br. 4) (emphasis omitted). Therefore, Appellants
conclude that one skilled in the art of “ESD devices would not combine Smith with
Avery since Smith does not relate to ESD devices” (Reply Br. 5). We disagree.
Clearly, Smith is related to ESD devices as Smith explicitly discloses that it
is related to “a semiconductor device having a stacked-gate that inhibits parasitic
bipolar effects during electrostatic discharge” (emphasis added) (Finding of
Fact 6). Furthermore, Appellants’ contention that the deeper doped region 80 of
Smith is associated with the stacked buffer and not the ESD structure is not
germane to the rejection of claim 2 in as much as the Examiner cites Smith for its
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