Ex Parte McKenney et al - Page 4

                  Appeal 2007-1600                                                                                         
                  Application 09/753,062                                                                                   

                                                FINDINGS OF FACT                                                           
                         The following Findings of Fact (FF) are shown by a preponderance of                               
                  the evidence.                                                                                            
                                                     The Invention                                                         
                         1. Appellants invented a method and system for efficiently                                        
                  handling high contention locking in a multiprocessor system (Specification                               
                  1).                                                                                                      
                         2. The processors of the multiprocessor system are organized in a                                 
                  hierarchical manner, wherein granting of an interruptible lock to a processor                            
                  is based upon the hierarchy (Specification 1).                                                           
                         3. Appellants’ Specification contains no specific definition of the                               
                  term “hierarchy.”                                                                                        
                                                        Kermani                                                            
                         4.  Kermani teaches an arbiter for a shared synchronous memory,                                   
                  comprising an arbitration module to select one of a plurality of requesting                              
                  agents (i.e., processors) for access to the shared synchronous memory (col.                              
                  2, ll. 46-49).                                                                                           
                         5. Kermani teaches a plurality of agents, each of which sends a                                   
                  memory access request to arbiter 102a, which includes a priority encoder                                 
                  190 (Fig. 2; col. 4, ll. 11-57).                                                                         
                         6. A memory access request by an agent (processor) is a digital                                   
                  signal that indicates that a particular agent desires access to the shared                               
                  synchronous memory (col. 4, ll. 33-45).                                                                  
                         7. If more than one memory access request signal is received by                                   
                  the arbiter during any one clock cycle, a winning agent is selected based on a                           


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