Appeal 2007-1648
Application 10/631,098
Examiner’s rejection is in error as “One can not map the solution of Au into
Ker and Brady, since it would not be operable nor possible to design and
implement.” (Br. 19). These arguments have not persuaded us of error in
the Examiner’s rejection. As discussed supra, Appellant has not presented
evidence to support the assertion that the circuits of Au and Ker can not be
implemented in SOI technology. Further, the Examiner has presented
evidence to show that the elements of Au and Ker can be implemented in
SOI technology. In the Examiner’s statement of the rejection the Examiner
equates the first and second circuit control network with Au’s SCRs (items
52 and 50 of figure 4b). (See Answer page 6). Appellant does not contest
this finding. Further, we note that Chatterjee teaches that implementing
SCRs in SOI technology can be accomplished using MOSFETs. (Fact 10).
Thus, Appellant’s arguments have not convinced us of error in the
Examiner’s rejection of claim 25.
CONCLUSION
Appellant has not shown that the Examiner erred in finding that the
circuit of Au could be implemented using SOI technology. Further, the
Appellant has not shown that the Examiner erred in finding that Au’s circuit
modified to be implemented in SOI teaches the body of the MOSFET being
floating with respect to the underlying substrate. Thus, we find no error in
the Examiner’s rejections, and we affirm the Examiner’s rejections of claims
14, 17, 18, and 24 through 36 under 35 U.S.C. § 103(a).
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv) (2006).
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