Ex Parte Steinecke et al - Page 2

                Appeal 2007-1711                                                                             
                Application 10/657,898                                                                       

                be done with "place+route" programs.  See Specification page 3, lines 11-16.                 
                Claim 1 is illustrative of the claimed invention, and it reads as follows:                   
                1.    An electronic device, comprising:                                                      
                a semiconductor chip having an active top side with a plurality of contact                   
                areas;                                                                                       
                said semiconductor chip having a plurality of metallization layers and a                     
                plurality of insulation layers configured alternately one above another on                   
                said active top side;                                                                        
                said plurality of metallization layers including topmost metallization layers                
                having a plurality of voltage supply structures and lower metallization layers               
                disposed underneath said topmost metallization layers and having a plurality                 
                of signal line structures;                                                                   
                said plurality of insulation layers formed with a plurality of passage contacts              
                connecting said plurality of voltage supply structures and/or said plurality of              
                signal line structures to said plurality of contact areas of said active top side;           
                said topmost metallization layers having ones of said plurality of passage                   
                contacts connected to said plurality of contact areas;                                       
                said topmost metallization layers having at least a first one of said plurality              
                of voltage supply structures for a low supply potential and a second one of                  
                said plurality of voltage supply structures for a high supply potential;                     
                said first one of said plurality of voltage supply structures being insulated                
                from said second one of said plurality of voltage supply structures;                         
                said first one of said plurality of voltage supply structures of said topmost                
                metallization layers having a grid of supply interconnects configured parallel               
                to one another;                                                                              
                said second one of said plurality of voltage supply structures of said topmost               
                metallization layers having a grid of supply interconnects configured parallel               
                to one another; and                                                                          

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