Appeal 2007-1968
Application 10/400,856
at least one primary processor,
a memory, and
at least one type register readable by at least one processor
selected from the group consisting of the primary
processor and an optional management processor of the
cell, the type register containing instruction set
architecture type information associated with the primary
processor of the cell;
wherein the primary processor of a first cell is of a first
Instruction Set Architecture type, and the primary
processor of a second cell is of a second Instruction set
architecture type;
wherein the system is capable of being partitioned into a
plurality of partitions, wherein each partition comprises
at least one said primary processor and is capable of
executing an operating system; and
wherein the system further comprises firmware capable of using
information in the type register of each of the plurality of
cells during system startup to ensure that all said primary
processors of each of the plurality of partitions have
compatible Instruction set architecture types.
The following reference is relied on by the Examiner:
Smith US 6,289,391 B1 Sep. 11, 2001
Claims 1 through 20 stand rejected under 35 U.S.C. § 102(b) as being
anticipated by Smith.
Rather than repeat the positions of the Appellant and the Examiner,
reference is made to the Brief for Appellant’s positions, and to the Answer
for the Examiner’s positions.
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