Appeal 2007-1968
Application 10/400,856
structures and different operating systems with different instruction set
architectures are taught.
Turning to the subject matter of dependent claim 2 argued briefly at
page 7 of the Brief, we agree with the Examiner’s approach to correlate
Smith’s IDL compiler in Figure 2 to the claimed feature, since such a
compiler must necessarily be embodied in a physical processor to the extent
a physical processor is recited in dependent claim 2. Note as well our
assessment of the prior art in the Specification earlier in this opinion. With
respect to compiler 102 in Smith, the separate server and client compilers
105 and 110 are also shown at Figure 2. Compilers necessarily operate at
the instruction set level. We also agree with the Examiner’s observation that
page 10 of the Answer that the extent of Appellant’s arguments with respect
to claim 2 is not actually claimed.
As to dependent claim 10, the Examiner takes the initial view at
page 6 of the Answer that the claimed field programmable gate array
(FPGA) is taught at column 3, lines 29 and 30. Although we regard this as a
weak basis for this feature, we are mindful that Appellant’s recognition of
the prior art field programmable cells already noted earlier in this opinion in
the prior art. Moreover, Appellant’s discussion of claim 10 at the top of
page 8 of the Brief recognizes that FPGAs were well known in the art as
structural elements of large integrated circuit structures with correlated
teachings associated with EEPROMs or EPROMs. The Examiner’s remarks
in the paragraph bridging pages 10 and 11 of the Answer are also persuasive
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