Appeal 2007-2127
Reexamination Control No. 90/006,621
Claim 1 is reproduced below (additions to the original patent claim
are underlined, see 37 C.F.R. § 1.530(f)(2)).
1. A method of preemptive multithreading operation of a
computer including a clock and a central processing unit having an
interrupt operation so as to provide for the execution of a program
having a task comprising a plurality of processing subtasks each
performed concurrently on alphanumeric data by a respective one of a
plurality of processing instruction threads of said program, said
method comprising
periodically actuating said interrupt operation in response to
said clock at predetermined time intervals to provide a
plurality of series of spaced timeslices with a respective
series of said plurality of series allocated for the
execution of each thread and with the timeslices of each
series of timeslices of said plurality of series interleaved
with the timeslices of at least one other series of said
plurality of series,
preempting an executing processing thread of said program in
response to each actuation of said interrupt operation so
as to terminate the timeslice of execution of said
executing thread and to take control of the central
processing unit away from said executing thread after the
latter has executed only a portion of its respective subtask
performed on said alphanumeric data,
passing said control of the central processing unit to another
processing thread of said same program and thereby
invoking said another thread to perform a next successive
portion of the respective subtask performed on said
alphanumeric data of said another thread during the next
successive timeslice of the respective series of timeslices
of said another thread,
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