Appeal 2007-2127
Reexamination Control No. 90/006,621
of the Z80 interrupt operation in the '604 patent (which is identical to the
description in the 1982 application) with the description in Zaks to show that
no interruption of the editor interrupt service routine is disclosed.
The '604 patent states that an interrupt signal is transmitted to "the
interrupt request pin INT* of the Z80 CPU" ('604 patent, col. 4, lines 28-29).
"Assuming that the interrupt of the processor is enabled, upon completion of
the present instruction the CPU's status pins IORQ* and M1* are activated
. . . ." (Id. at col. 4, lines 30-32). Compare Zaks, page 500 ("Essentially, the
Z80 will respond to the interrupt by generating an IORQ (and an M1 signal),
and then do nothing, except wait."). The '604 patent states that the IORQ*
and M1* signals are used to "form the INTA (interrupt acknowledge) signal"
(col. 4, lines 30-34) which causes an external interrupt vector register to put
an RST instruction on the data bus. ('604 patent, col. 4, lines 34-37).
Compare Zaks, page 500 ("It is the responsibility of an external device to
recognize the IORQ and M1 (this is called an interrupt acknowledge or
INTA) and to place an instruction on the data-bus. . . . Typically, an RST or
a CALL instruction is placed on the bus.").
The '604 patent states ('604 patent, col. 4, lines 38-49):
The RST instruction is then input to and executed by the Z80
CPU, causing the latter to push the contents of the program counter
onto the stack, and further causing the CPU to jump to a
predetermined location in low memory. This location stores a
"vector" or three-byte JMP (jump) instruction to an interrupt service
routine. The latter includes the editor as well as a subroutine to store
the contents of the CPU registers. Control of the CPU is then retained
by the editor until either a character has been entered into the source
code buffer or an editing operation has been completed.
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