Appeal 2007-2127
Reexamination Control No. 90/006,621
Compare, Zaks, page 500:
Typically, an RST or a CALL instruction is placed on the bus. Both
of these instructions automatically preserve the program counter in the
stack, and cause branching to a specific address. The advantage of the
RST instruction is that it resides within a single byte, i.e., it executes
rapidly. Its disadvantage is to branch to only one of eight possible
locations in page zero (addresses 0 through 255). . . .
The '604 patent describes that the CPU is vectored to the interrupt
service routine, which includes a subroutine to perform the SAVE
REGISTERS procedure and execute the editor program ('604 patent, col. 5,
lines 11-15). When the editor is finished ('604 patent, col. 5, lines 23-32):
The interrupt service routine then jumps to its subroutine to
perform the RESTORE REGISTERS procedure whereby the registers
of the CPU are restored to their original values at the instant of the
interrupt.
The ENABLE INTERRUPT instruction (EI) is then executed
by the CPU so that the latter may respond to the next interrupt.
Finally, the RET instruction is executed so that the CPU may
RETURN TO COMPILER. The compiler resumes execution from
the point where it was interrupted.
Compare, Zaks, pages 500-501:
Note that once the interrupt processing starts, all further
interrupts are disabled. [Interrupt flip-flops] IFF1 and IFF2 are
automatically set to "0". It is then the responsibility of the
programmer to insert an EI instruction (Enable Interrupt) at the
appropriate location within his program if he wishes to enable
interrupts, and, in any case, before returning from the interrupt.
Thus, once the interrupt processing of the editor program starts,
further interrupts are disabled, i.e., a clock-signal will not cause an interrupt.
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