Appeal No. 94-4061
Application 07/659,683
result in none of the AND-gates 30.1 to
30.4 having both of its inputs at level
1. Consequently, the output of the OR-
gate 32 will remain at level 0 whereby
the output of the inverter will remain
at level 1. Thus, both inputs of the
AND-gate 40 will be at level 1 (active)
whereby the output of the gate 40 will
go to level 1 and this level will be
passed to the reset input RS of the
microprocessor 10, via the OR-gate 42,
so as to reset the micro-processor.
[Specification, pages 11-12]
This relationship between the shift register and the output lines
of the microprocessor is also recited in the claims. Claim 3,
which is dependent on claim 9, recites that the microprocessor
apparatus comprises a "logic means for applying a reset command
to a reset input of said microprocessor means in response to the
occurrence of said activation signals on said plurality of output
lines other than in said predetermined sequence." Claim 6, which
is dependent on claim 3, recites that the logic means comprises a
"recirculating shift register means" and a "plurality of AND
function means" which produce a:
"predetermined logic signal at an output thereof upon
the provision of a predetermined logic signal at each
of a respective one of said output lines and a
respective stage of said shift register."
-8-
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