Appeal No. 94-4061
Application 07/659,683
The output of BIT 2 is a clocking signal and is
connected to shift register 20. The pattern stored in the shift
register 20 is reloaded each time a clocking signal is output at
BIT 2 and as a result shift register 20 sends a high signal to
counter 25 which clears the counter (Col. 6, lines 6-13). If the
clocking signal is not output from BIT 2 at a sufficient rate,
the counter will count up and expire (Col 6, lines 18-23). If
the counter expires, a signal will pass to OR gate 18 which will
thus reset processor 10 (Col. 6, lines 44-48).
The bit pattern manipulator includes a shift register
15 which is a recirculating shift register which is initially
loaded with a predetermined bit pattern (Col. 8, lines 7-14).
When a watchdog instruction is received and decoded by the
processor 10, the signal output at BIT 2 is set to low (Col. 7,
lines 26-39). In addition, the bit pattern at BIT 1 is set to
coincide with a specific predetermined masked bit (most
significant bit) of the bit pattern stored in a first register AL
of processor 10 (Col. 7, lines 33-39). The bit pattern in AL is
then manipulated. In the embodiment disclosed in Owens, the bit
pattern is shifted to the right (Col. 7, lines 41-46). BIT 2 is
then set to high and outputs a clocking signal to shift register
15 which causes shift register 15 to shift the stored bit pattern
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Last modified: November 3, 2007