Appeal No. 94-4061
Application 07/659,683
Turning next to the rejection of claims 3-7, 9, 12, 13,
15 and 16 under 35 U.S.C. § 103 over Gercekci and Proto, we find
that Gercekci discloses a processor 2 having a first memory 4
which holds the primary operating routine of the microprocessor
(Col. 2, lines 27-29). The operating routine includes predeter-
mined addresses for instructions to reset a timer 10 (Col. 2,
lines 31-33). In order to prevent false resetting of the timer
10, a watchdog timer 8 is provided which includes a second memory
12 which stores the predetermined addresses and a comparator 18
which compares the address of each reset instruction with the
addresses stored in second memory 12 (Col. 3, lines 7-11). If
the addresses coincide, comparator 16 outputs a signal to AND
gate 22 which together with the RTR (reset timer request) signal
is enabled and the timer is reset (Col. 3, lines 8-12). Gercekci
discloses that if the reset instruction is located at an address
other than the next predetermined address, the AND gate would not
be enabled and therefore would not produce a signal to reset the
timer (Col. 3, lines 35-48).
The examiner, recognizing that Gercekci does not
disclose a decoder that generates activation signals that are
input to shift register means, relies on Proto for teaching a
method of using shift registers updated by activation signals
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