Appeal No. 94-4061
Application 07/659,683
(21) to determine the validity of a sequence of instructions
executed (Examiner's Answer, pages 5-6).
We find that Proto discloses an apparatus for verifying
the execution of a sequence of coded instructions which includes
a processor 10, a memory 11 and a sequence error detector 20
(Fig. 1). Sequence error detector 20 monitors the sequence of
instructions stored in memory 11 through lines 15 from which
processor 10 reads instructions from memory 11 (Fig. 1, Col. 3,
lines 51-53). Sequence error detector 20 includes a reference
checkword storage 31, a comparator 32, and shift register 37
having stages R , R etc. Shift register 37 along with adders1 2
40 modify the binary sequence received from the processor and
form a checkword which is sent to comparator 32 which compares
the checkword received from stages R , R etc. and adders 40 with1 2
the reference checkword provided from reference checkword storage
31 (Col. 4, line 49-Col 5, line 21). If the two words are not
the same, indicating that the instructions from processor 10 are
out of sequence, the comparator outputs a signal which indicates
that there is an error (Col. 4, lines 9-13, Col. 5, lines 23-25).
The examiner stated:
It would have been obvious to a
person of ordinary skill in the art at
the time the invention was made that the
means of checking valid sequence of
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