Appeal No. 94-4061
Application 07/659,683
one place to the right so that one bit (most significant bit) is
shifted off and recirculated and also applied to NOR gate 16
(Col. 8, lines 13-15). NOR gate 16 is also coupled to BIT 1
(whose bit pattern has also been shifted to the right) (Col. 8,
lines 16-19). If the two inputs to NOR gate 16 are not the same,
NOR gate 16 is enabled (Col. 8, lines 18-20). The NOR gate 16
together with the clocking signal enables AND gate 17 and the
processor 10 is reset (Col. 8, lines 19-21). As long as the
processor 10 is operating in a predetermined sequence which
corresponds to the bit pattern stored in shift register 15 and
the counter has not counted up, the processor 10 will not be
reset.
Recognizing that Owens does not disclose a "watchdog
instruction decoder means connected to an output of said
microprocessor means" as recited in claim 9, the examiner states:
whether the decoder lies inside or
outside the microprocessor is not
critical to the invention as long as the
means properly function as a detector of
a watchdog instruction and any means
including a software CALL ROUTINE
execution means inside a microprocessor,
that detects the watchdog instruction
and generates activation signals, would
be equivalent [Examiner's Answer, page
9, emphasis added].
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