Appeal No. 94-4061
Application 07/659,683
decoder 16 detects a watchdog instruction, it activates one of a
plurality of output lines L1 to L4 (Page 7, lines 22-24).
Appellant's specification also discloses that each of the
watchdog instructions is different and that address decoder 16
activates one of the output lines L1 to L4 in response to the
watchdog instruction (Page 7, lines 24-25).
Owens does not disclose that the watchdog instructions
are decoded by detecting an address portion of an instruction and
responding to instructions which are watchdog instructions by
activating a plurality of output lines depending on the watchdog
instruction received. In contrast, each time a watchdog
instruction is decoded, BIT 1 is activated and BIT 2 is
deactivated. There is no basis for finding that Owens discloses
an equivalent of the watchdog decoder structure disclosed in
appellant's specification. In addition, the examiner has not
articulated any motivation for placing the decoder outside of the
microprocessor. Nor has the examiner provided any factual basis
for concluding that the location of the decoder is not critical.
In view of the foregoing, we will not sustain the rejection of
claims 3-7, 9, 12, 13, 15 and 16 under 35 U.S.C. § 103 as being
unpatentable over Owens.
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