Ex parte MIYABAYASHI - Page 2

          Appeal No. 95-1527                                                          
          Application No. 07/862,066                                                  
               Appellant’s Claim 1 is reproduced as follows:                          
                    1.   A read-out circuit for use with a semiconductor              
                    memory device, said read-out circuit comprising:                  
                         first selecting means for selectively reading at             
                    least one datum from a plurality of memory means;                 
                         first data storing means for storing the data                
                    read out by said selecting means;                                 
                         transferring means for transferring the data                 
                    stored in said first data storing means in                        
                    synchronism with an external clock signal;                        
                         second data storing means for storing the data               
                    transferred from said transferring means;                         
                         second selecting means for selectively                       
                    outputting to an output port the data stored in said              
                    second data storing means; and                                    
                         presetting means for presetting the voltage                  
                    level of the line onto which said first selecting                 
                    means reads out data.                                             

               The Examiner’s Answer relies on admitted prior art and                 
          the following prior art reference:                                          
                    Lam et al. (Lam)         4,731,758           Mar. 15,             



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