Appeal No. 95-3798
Application 08/063,968
coupled in parallel to the conductance path of one of
said current mirror transistors, said hysteresis stage
responsive to a conductance state of one of said
differential mode transistors for enabling current
through said hysteresis stage.
Claim 8 specifies that the hysteresis stage comprises a
hysteresis mirror transistor having a conductance path in series
with the conductance path of a switching transistor. But claim 8
does not require that the conductance paths of the current mirror
transistors be individually coupled to the conductance paths of
the differential mode transistors.
Opinion
We do not sustain the rejection of claims 1-16 under
35 U.S.C. § 102(b) as being anticipated by Sakai.
In Sakai's Figure 5, the examiner correctly identified
(Paper No. 9, pages 2-3): (1) transistors Q3 and Q4 as a pair of
transistors arranged in differential mode, (2) current source Is
as a means for providing constant current into the conductance
paths of the pair of differential transistors, and (3)
transistors Q6 and Q9 as the current mirror transistors whose
conductance paths are individually coupled to the conductance
paths of Q3 and Q4. These finding have not been challenged.
But the examiner has incorrectly identified (Paper No. 9,
page 3) transistor Q5 as a hysteresis stage satisfying claims 1
-4-
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