Appeal No. 95-3798
Application 08/063,968
and 8. In that regard, both claims 1 and 8 require a hysteresis
stage having a "conductance path coupled in parallel to the
conductance path of one of said current mirror transistors." In
item D on page 3 of the final Office action (Paper No. 9), the
examiner found that Sakai discloses transistor Q5 which
constitutes "a hysteresis stage providing a parallel conductance
path." It appears that the examiner has ignored, omitted, or not
accounted for that claim language concerning the conductance path
of the hysteresis stage, i.e., that it be "coupled in parallel to
the conductance path of one of said current mirror transistors."
In applying Sakai, the examiner specifically referred to and
relied on the Figure 5 embodiment of Sakai as the basis of his
findings and analysis (Paper No. 9, page 2). Accordingly, our
discussion of Sakai is also directed to its Figure 5 embodiment.
Even assuming that the examiner has found that the
conductance path of transistor Q5 is coupled in parallel to the
conductance path of one of the current mirror transistors Q6 and
Q9, the finding is incorrect. With respect to Sakai, we do not
find that the conductance path of transistor Q5 is coupled in
parallel to the conductance path of either current mirror
transistor Q6 or Q9.
The term "conductance path" is not explicitly defined in the
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