Appeal No. 95-4084
Application 07/992,648
writing said coefficient data stored in said transfer buffer
into a coefficient data memory by said read cycle steal at an
execution stage in said processing unit.
The references relied on by the examiner are:
Garrett et al. (Garrett) 4,991,217 Feb. 5, 1991
Yamaki et al. (Yamaki) 5,218,710 June 8, 1993
(filed Jan. 22, 1990)
Claims 1 and 2 stand rejected under 35 U.S.C. § 103 as being
unpatentable over Yamaki in view of Garrett.
Reference is made to the briefs and the answers for the
respective positions of the appellants and the examiner.
OPINION
We have carefully considered the entire record before us,
and we will reverse the obviousness rejection.
The examiner is of the opinion that Yamaki discloses the
claimed method, but did not "specifically disclose the steps of
discriminating whether an instruction is a read instruction or
writing data into a coefficient data memory by said read cycle
steal" (Answer, pages 3 and 4). For a teaching of the missing
steps, the examiner turned to the dual processor speech
recognition system teachings of Garrett. The examiner indicates
(Answer, page 4) that:
Garrett et al. disclosed the steps of discriminating
whether an instruction is a read instruction from a
value of said program counter (col. 19, line 30, et
seq.) and writing data into a coefficient data memory
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