Appeal No. 95-4084
Application 07/992,648
by said read cycle steal (col. 28, line 19, et seq.).
It would have been obvious to one of ordinary skill in
the art at the time of Appellant's [sic] invention to
incorporate Garrett et al.'s cycle steal sequencer into
the Yamaki et al. system because Garrett et al.'s cycle
steal sequencer would increase the throughput of the
Yamaki et al. system by allowing for the transfer of
coefficient data upon the detection of a read
instruction.
Appellants acknowledge the structural similarities between
the disclosed system and the system disclosed in Yamaki, but
argue that the method by which the Yamaki system replaces
coefficient data is very different from the method recited in the
claims (Brief, page 9). Appellants also argue that "Yamaki fails
to suggest a read cycle steal as recited in claim 1, or anything
equivalent" (Brief, page 13), and that "Yamaki nowhere discloses
scheduling different DSP functions during particular stages of
the three machine cycles (read or fetch stage, decode stage,
execute stage) used in pipeline processing" (Brief, page 14).
During the transfer of coefficient data (column 9, lines 18
through 63) in Figure 1 of Yamaki, the microcomputer supplies a
muting control instruction to sequence controller 18 which then
places the system in a muting condition via muting switch circuit
30. The microcomputer then reads a sequence control program,
coefficient data, and other data corresponding to a newly
selected sound field from ROM. The sequence control program is
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