Appeal No. 95-5012
Application 08/076,876
The disclosed invention relates to time shared use of buses
within a computer system.
Claim 1 is illustrative of the claimed invention, and it
reads as follows:
Claim 1. In a computer system having timed shared use of
buses to reduce the number of required pins for devices within
said computer system, comprising, in combination:
Central Processing Unit (CPU) means having at least one
address bus, at least one data bus, at least one memory
input/output, and at least one CPU control bus coupled thereto
for sending and receiving information;
at least one memory input/output means coupled to a first
portion of said address bus for sending and receiving at least
one of address information and data information;
at least one input/output only means coupled to a second
portion of said address bus for sending and receiving at least
one of address information and data information; and
multiplex system controller means coupled to said CPU means
and to said address bus and having multiplex control bus means
coupled to both said memory input/output means and to said
input/output only means for time sharing said address bus of said
CPU means in order to sequentially transfer groups of at least
address and data information to said memory input/output means
and said input/output only means comprising, in combination:
state machine means coupled to said multiplex control bus
means and to said CPU control bus for controlling said multiplex
system controller means;
address latch means coupled to said state machine means and
to said address bus for temporarily storing address information;
and
a plurality of multiplexer means each coupled to said
address latch means, said data bus, said state machine means, and
to a Direct Memory Access (DMA) controller for transferring data
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Last modified: November 3, 2007