Appeal No. 95-5012
Application 08/076,876
to said data bus and to said address bus in response to control
signals from said state machine means.
The references relied on by the examiner are:
Pohlman et al. (Pohlman) 4,112,490 Sept. 5, 1978
Baker et al. (Baker) 4,286,321 Aug. 25, 1981
Claims 1, 3 through 9, 19, 20 and 23 through 27 stand
rejected under 35 U.S.C. § 103 as being unpatentable over Pohlman
in view of Baker.
Reference is made to the brief and the answer for the
respective positions of the appellants and the examiner.
OPINION
We have carefully considered the entire record before us,
and we will reverse the obviousness rejection of claims 1, 3
through 9, 19, 20 and 23 through 27.
With respect to independent claims 1 and 19, the examiner is
of the opinion (Final rejection, pages 5 and 6) that:
Pohlman teaches a CPU connected to a data bus, an
address bus, a memory I/O signal line, and a control
bus (Figure 2). Pohlman teaches a memory I/O means
coupled to a first portion of said address bus (Figure
2). Pohlman teaches an I/O only means (Column 4 lines
28-31), and a multiplex controller as part of his CPU
for time sharing said address bus of said CPU in order
to sequential [sic, sequentially] transfer groups of at
least address and data information to said memory I/O
means and said I/O only means (Column 2 lines 24-29).
Pohlman teaches a state machine means coupled to said
multiplex control bus means and to said CPU control bus
for controlling said multiplex system controller means
(Control + Timing item 42). Pohlman teaches address
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