Appeal No. 95-5012
Application 08/076,876
latch means coupled to said state machine means and to
said address bus for temporarily storing address
information (item 94 includes address and data buffers
as well as multiplexers also Figure 1 item 136).
Pohlman also teaches a DMA controller for transferring
data to said data bus and to said address bus in
response to control signals from said state machine
means (Figure 15 item 240, and Column 18 lines 1-25).
Pohlman does not teach a plurality of multiplexer means
each coupled to said data bus, said address latch, said
state machine means, and to the DMA controller.
Pohlman only teaches one multiplexer attached to all
the items mentioned above.
The computer system in Figure 15 of Pohlman discloses a CPU
20 that has an address bus 48, a multiplexed address/data bus 50,
and a control bus 52. A memory I/O device 242 or 262 is
connected to all three buses, whereas I/O only peripheral devices
are only connected to the multiplexed address/data bus 50 and the
control bus 52 via interrupt controller 238. A DMA 240 is shown
connected between the CPU and the three buses. Pohlman states
(column 5, lines 20 through 25) that a state generator is part of
the timing circuitry portion 30 of the CPU 20 (Figure 1). In
Figure 2 of Pohlman, latches 244 and 264 are shown as part of
memory I/O devices 242 and 262, respectively.
We agree with the examiner that Pohlman discloses a state
machine means, an address latch means, a DMA controller, and a
multiplexer (not shown) in CPU 20 to handle the time multiplexing
between address and data on bus 50, but we do not, however, agree
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