Appeal No. 96-2607
Application 08/001,865
claims 1 through 10, all of the claims pending in the present
application.
The invention relates to a method and system for enhanced
instruction dispatch in a superscaler processor system
utilizing independently accessed intermediate storage. On
pages 13 and 14 of the specification, Appellants disclose that
Figure 3 illustrates the utilization of intermediate storage
buffers within the superscaler processor system of Figure 1,
in accordance with their invention. The plurality of
intermediate storage buffers 20 are connected to one
independent bus 64. Each of a plurality of execution units
24a, 24b and 24c are coupled to each of the multiple
independent buses 64. Thus, when data is generated by the
execution of an instruction within an execution unit, the
execution unit places that data on a bus corresponding to a
designed intermediate storage buffer which has been specified
as a destination for that data, where the data is temporarily
stored. On page 15 of the specification, Appellants disclose
that the advantage of this arrangement is the
elimination of the need to store the data in a buffer and then
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