Appeal No. 96-2607
Application 08/001,865
The Examiner further argues on page 7 of the answer
that Lawrie teaches coupling each of said plurality of
intermediate storage buffers to all of said plurality of
execution units via an independent bus wherein each
independent bus is associated with a single one of said
plurality of intermediate storage buffers. The Examiner
reasons that Lawrie teaches this limitation because Lawrie
shows in Figure 3 a storage device coupled to all of the
plurality of arithmetic units via a bus.
Upon a careful review of Lawrie, we find that the
reference fails to teach the Appellants’ recited limitation of
coupling
each of said plurality of intermediate storage buffers to all
of said plurality of execution units via an independent bus
wherein each independent bus is associated with a single one
of said plurality of intermediate storage buffers. In column
1, Lawrie teaches that the object of his invention is to
provide non-conflicting linear vector storage of a
multidimensional matrix in
a parallel memory computer system. In column 2, lines 49-58,
Lawrie teaches that the present invention is understood by
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