Appeal No. 96-2607
Application 08/001,865
considering a multidimensional matrix 11 pierced by a linear
vector 13 shown in Figure 1. Lawrie states that the invention
provides a method and apparatus for accessing in parallel all
matrix elements along the vector 13. In column 3, lines 1
through 14, Lawrie teaches that Figure 3 shows the storage
apparatus of their invention. The storage apparatus generates
two indexing tags, T(D) and N(m). Tag T(D) aligns a
particular memory 17 with a particular processor 19 and tag
N(m) addresses memory 17. In column 4, line 56, through
column 5, line 35, Lawrie teaches that the storage apparatus
provides linear vector storage for a three dimensional matrix.
It is clear that the storage apparatus is not providing the
function of bus buffering as claimed in Appellants’ claims.
Therefore, we fail to find that the references teach or
suggest coupling each of said plurality of intermediate
storage buffers to all of said plurality of execution units
via an independent bus wherein each independent bus is
associated with a single one of said plurality of intermediate
storage buffers as recited in Appellants’ claims. We are not
inclined to dispense with proof by evidence when the
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