Ex parte KAHLE et al. - Page 3




          Appeal No. 96-2607                                                          
          Application 08/001,865                                                      


          thereafter access that data from the buffer.  The ability to                
          retrieve data directly from the bus will significantly                      
          increase the operation speed of the processing system.                      
               The independent claim 1 is reproduced as follows:                      
               1.   A method for enhanced instruction dispatch                        
               efficiency in a superscalar processor system capable of                
               fetching an application specified ordered sequence of                  
               scalar instruc-tions and simultaneously dispatching a                  
               group of said scalar instructions to a plurality of                    
               execution units, said method comprising the steps of:                  
                         providing a plurality of intermediate storage                
                    buffers within said superscalar processor system;                 
                         coupling each of said plurality of intermediate              
                    storage buffers to a11 of said plurality of                       
                    execution units via an independent bus wherein each               
                    independent bus is associated with a single one of                
                    said plurality of intermediate storage buffers;                   
                         dispatching selected ones of said group of                   
                    scalar instructions to selected ones of said                      
                    plurality of execution units on an opportunistic                  
                    basis; and                                                        
                         transferring a result of execution of each of                
                    said dispatched scalar instructions from one of said              
                    plurality of execution units to a designated one of               
                    said plurality of intermediate storage buffers via                
                    an associated independent bus, wherein said results               
                    may be stored without contention for access among                 
                    said plurality of execution units and wherein said                
                    result is available to each of said plurality of                  
                    execution units.                                                  
                    The Examiner relies on the following references:                  

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