Appeal No. 94-0809
Application 07/707,365
The examiner finds (Ans., pp. 4-5, bridging para.):
Nishizaka teaches a process of forming an integrated
circuit substantially as claimed including forming an
oxide layer 3 and insulation regions 2 on a substrate 1,
depositing a polysilicon layer 4 on said oxide film 3,
forming an oxidation film 5 and a silicon nitride layer 6 on
said polysilicon layer 4 (Fig. 3(A)), etching said layers 4,
5, and 6 to form gate structure having insulation sidewalls
9, a gate electrode 4, and insulation layers 5 and 6 on top
of said gate electrode 4 (Fig. 3(C)), forming polysilicon
plugs 10 between gate electrode 4 and insulation region 2
(Fig) 3(E)), doping impurities into said polysilicon
plugs 10 (col.4, lines 10-20), oxidizing surface of said
polysilicon plugs 10 to form an oxidation layer 11 on top
of said plugs 10, connecting a source electrode 16 to said
polysilicon plugs 10 (col. 5, lines 1-4 and Fig. 3(L)),
etching said oxidation film 5 and said nitride layer 6
to expose a portion of gate electrode 4, and forming
an interconnection layer 12 connected to said exposed
electrode 4.
Appellants do not contest these findings. Moreover, after
examining Nishizaka’s disclosure, we cannot conclude with
confidence that the examiner’s findings are clearly erroneous.
Fig. 3A shows that “a p-semiconductor substrate 1 is
selectively oxidized on a predetermined region to provide
a field oxidation film 2" (col. 3, l. 53-55), “a gate oxidation
film 3 . . . is formed . . .” (col. 3, l. 55-56), “a poly-
crystalline silicon layer 4 . . . is grown on the substrate 1
having the gate oxidation film 3 thereon” (col. 3, l. 57-60),
“a mask oxidation film 5 . . . is formed on the polycrystalline
silicon layer 4" (col. 3, l. 60-62), and “a silicon nitride film
6 is formed on the mask oxidation film 5" (col. 3, l. 63-65).
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