Appeal No. 94-0809
Application 07/707,365
Figs. 3B-C depict gate structures fabricated when the
structure of Fig. 3A is selectively etched to form a repeat of
gate structures and separating trenches positioned between
insulating regions (not depicted).
Fig. 3D depicts “polysilicon plugs” made by applying
polycrystalline silicon over the entire substrate and filling the
trenches. Nishizaka’s polycrystalline silicon-filled trenches
may be implanted or “doped with impurities to be the same
conduction type as that of the substrate 1” (Nishizaka, col. 4,
l. 16-18).
Figs. 3E-F show that “the polycrystalline silicon layer 10
is etched back . . . by use of the silicon nitride 6 as a mask”
for the gate structure (col. 4, l. 21-23) and “insulating
oxidation films 11 are formed on the top surface of the
polycrystalline silicon layer 10 and on the sides of the
polycrystalline silicon layer 4" (col. 4, l. 23-26) and on the
silicon nitride 6 used as a mask.
However, we can and do find that Nishizaka’s formation of
insulating oxidation films 11 on the top surface of the
polycrystalline silicon layers 10 and on the silicon nitride 6
mask does not cause the impurities with which polycrystalline
silicon layer 10 may be doped “to diffuse into the substrate to
form source/drain regions of a field effect transistor.” We note
- 8 -
Page: Previous 1 2 3 4 5 6 7 8 9 10 11 12 13 Next
Last modified: November 3, 2007