Ex parte UEDA et al. - Page 2




            Appeal No. 94-2080                                                                         
            Application 07/982,068                                                                     

            canceled.  No claim has been allowed.                                                      

                             References relied on by the Examiner                                      

            Castrucci et al. (Castrucci)  3,785,886                     Jan. 15, 1974                  
            Wickstrom                           4,070,690               Jan. 24, 1978                  
            Imaizumi et al. (Imaizumi)          4,278,987               Jul. 14, 1981                  
                                    The Rejections on Appeal                                           
                  Claims 7-11 stand finally rejected under 35 U.S.C. § 112,                            
            first paragraph, as being without written description in the                               
            specification.                                                                             
                  Claims 7-11 stand finally rejected under 35 U.S.C. § 103 as                          
            being unpatentable over Wickstrom, Imaizumi, and Castrucci.                                
                                           The Invention                                               
                  The invention is directed to a vertically oriented insulated                         
            gate field effect transistor formed on a semiconductor substrate                           
            having a (100) principal plane.  A rectangular recess is formed                            
            such that at least two side walls thereof make a 45 degree angle                           
            against the (01ù) plane of the substrate.  Claim 10 appears the                            
            broadest and is reproduced below:                                                          
                  10. A power vertical insulated gate FET comprising:                                  
                        a silicon substrate of high concentration n-type                               
                        conductivity having a principal (100) plane,                                   
                        an epitaxially grown lower concentration n-type                                
                        epitaxial layer on said substrate,                                             

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