Appeal No. 95-3159
Application No. 08/064,678
independently enable said active vector calculation units to
access said main memory and to thereby execute a vector
calculation by use of said active vector calculation units
in the pipeline fashion.
The references relied on by the examiner are:
Hoshino et al. (Hoshino) 4,949,292 Aug. 14, 1990
(Section 102(e) date: Jan. 11, 1989)
Inagami et al. (Inagami) 5,109,499 Apr. 28, 1992
(filed Aug. 29, 1988)
Claims 1, 3 through 6 and 8 through 12 stand rejected under
35 U.S.C. § 103 as being unpatentable over Inagami in view of
Hoshino.
Reference is made to the briefs and the answer for the
respective positions of the appellant and the examiner.
OPINION
We have carefully considered the entire record before us,
and we will reverse the obviousness rejection of claims 1, 3
through 6 and 8 through 12.
Inagami is directed to a common vector register 100 (Figures
1 and 2) that is used by a plurality of vector processors 200
through 203 in a vector multiprocessor system. The examiner
correctly concluded (Answer, page 3) that Inagami is completely
silent concerning a “plurality of vector calculation units” in
each of the vector processors. According to the examiner
(Answer, page 3), “Hoshino et al. taught a vector processing unit
3
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