Appeal No. 95-3159
Application No. 08/064,678
wherein the processing unit included a plurality of vector
calculating units, such as odd term calculating circuit, even
term calculating circuit, multiplication circuit, adder
circuit...etc. (e.g. see col. 4, lines 6-31).”
Even if we assume for the sake of argument that the
plurality of circuits in the vector processing unit of Hoshino
are a “plurality of vector calculation units,” the claimed
limitations of “individually controlling said vector calculation
units in each of said processors to selectively change the number
of active vector calculation units in each of said processors”
(claims 1 and 3 through 5), and “changing the number of the
currently active vector calculation units in accordance with said
active indication signal” (claims 6 and 8 through 12) can never
be met by Hoshino because the plurality of circuits are
“simultaneously” operated to solve a recurrent equation
(column 6, lines 53 through 55). Stated differently, the number
of currently active vector calculation units in Hoshino can never
be changed (Brief, page 6). Thus, the obviousness rejection of
claims 1, 3 through 6 and 8 through 12 is reversed.
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Last modified: November 3, 2007