Appeal No. 95-3637
Application 07/968,736
The Rejections on Appeal
Claims 1-4 and 9-15 stand finally rejected under 35
U.S.C.
§ 103 as being unpatentable over Lee.
The Invention
The invention is directed to an integrated EEPROM wherein
the select and floating gates are each formed from polysilicon
sidewalls. Claims 1 and 9 are independent claims and are
reproduced below:
1. An EEPROM cell comprising a dual-gate transistor
having a select gate, a floating gate and a control gate
disposed on top of the floating gate, said gates being
disposed above a channel and between a source and drain, said
select gate being separated vertically from said channel by a
gate oxide, said floating gate being separate vertically from
said channel by a tunnel oxide and said control gate being
separated vertically from said floating gate by a second layer
of insulator; characterized in that:
said select and floating gates are each formed from
polysilicon sidewalls and are separated horizontally by a thin
vertical insulating member.
9. An integrated circuit EEPROM comprising:
input/output means for passing data into and out from
said EEPROM;
2
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