Appeal No. 95-4154
Application 08/122,193
References relied on by the Examiner
Asano et al. 4,719,369 Jan. 12, 1988
(Asano)
Anderson 5,039,874 Aug. 13, 1991
(filed Mar. 15, 1990)
The Rejections on Appeal
Claims 30, 31 and 35-37 stand finally rejected under
35 U.S.C. § 102(b) as being anticipated by Asano.
Claims 32, 33 and 43 stand finally rejected under 35 U.S.C.
§ 103 as being unpatentable over Asano and Anderson.
Claims 34, 38, 39, 40 and 45 stand finally rejected under
35 U.S.C. § 102(b) as being anticipated by, or in the
alternative, under 35 U.S.C. § 103 as being unpatentable over
Asano.
Claims 30, 38 and 43 are the only independent claims.
The Invention
The invention is directed to an integrated circuit having a
plurality of output buffers each with an output coupled to the
output terminal of the integrated circuit. Each output buffer is
coupled between the input terminal of the integrated circuit and
the output terminal in response to a control signal which is
varied in response to an impedance selection input asserted at an
input pin of the integrated circuit. A user can select
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