Appeal No. 96-1432
Application 08/232,600
a write through with no write allocate approach, a cache memory controller in the cache
memory system reduces cache flushes on write cache misses by performing cache flushes only for
cacheable physical memory locations.
Claim 7 is illustrative of the claimed invention, and it reads as follows:
7. An improved computer system comprising a central processing unit (CPU) coupled to a
cache memory and a main memory executing a plurality of processes, wherein cache hits/misses are
determined based on virtual addresses, some of said virtual addresses are alias addresses to each
other, and cacheability of memory locations is determined as an integral part of virtual address to
physical address translations, said improvement comprising an improved cache memory controller
coupled to said CPU, said cache memory, and said main memory, that allows said CPU to update said
cache and main memory with an improved write through with no write allocate approach that reduces
cache flushes on write cache misses by waiting for the results of said cacheability determinations, the
results of said cacheability determinations being available after the results of the corresponding cache
hit/miss determinations, then without detecting for alias addresses of the virtual addresses, conditionally
performing cache flushes for cache write misses only for cacheable memory locations.
The reference relied on by the examiner is:
Frink et al. (Frink), “A Virtual Cache-Based Workstation Architecture,” 2nd IEEE Conference on
Computer Workstations, Computer Society Press of the IEEE, 1988, pages 80 through 87.
Claims 1 through 9 stand rejected under 35 U.S.C. § 103 as being unpatentable over Frink.
Reference is made to the briefs and the answer for the respective positions of the appellant and
the examiner.
OPINION
2
Page: Previous 1 2 3 4 5 Next
Last modified: November 3, 2007