Appeal No. 96-1432
Application 08/232,600
We have carefully considered the entire record before us, and we will reverse the obviousness
rejection of claims 1 through 9.
The write policy normally used by the cache disclosed by Frink is write through, with write
allocate (page 81, column 2). In a discussion of virtual address synonyms, Frink states (page 82,
column 2) that “[v]irtual address synonyms, or aliases, exist when two or more virtual addresses point
to the same physical data.” According to Frink (page 83, columns 1 and 2):
Another problem with virtual address synonyms exists if only a write-through without
write-allocate policy is used. In this situation, Process 1 reads from address VA1, and
the data is inserted in the cache at line L1. Process 2 then writes to address VA2
(which is a synonym to VA1 and indexes to line L1), but L1 is not affected because a
write miss occurs as the result of a cache tag mismatch. When Process 1 reads VA1, it
accesses stale data from line L1 instead of the new data that’s been written by Process
2.
To solve this problem, a write miss must do one of two things: invalidate the indexed
cache entry, or update the entry to contain the new data.
According to the examiner (Answer, page 3), “‘A Virtual Cache-Based Workstation
Architecture’ suggests that it was known to condition the flushing of a cache memory location on a
write miss based on a cacheability determination at p. 82, c. 2, ll. 31-34 and p. 83, c. 2, ll. 7-11.”
Appellant argues (Brief, pages 7 through 9) that:
Although Virtual Cache discloses a virtually addressed cache, it does not teach
or suggest conditioning the flushing of the affected cache line upon the determination of
cacheability after a write miss. Virtual Cache merely teaches verifying cacheability
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Last modified: November 3, 2007