Appeal No. 96-1432
Application 08/232,600
following a read miss rather than a write miss. Virtual Cache, p. 82 column 2 lines 4-
17, and footnote. . . .Indeed, in a subsequent discussion of write misses, Virtual Cache
does not suggest checking the cacheability bit of a physical memory location
before invalidating a cache line. For example, after a write miss, Virtual Cache teaches
that a cache line be replaced by the data that has just been written to memory, in effect
flushing the previous cache line. Virtual Cache, p. 82 lines 31-34.
Even when it undertakes a discussion of synonymous virtual addressing (aliases), Virtual
Cache teaches away from conditioning a cache line flush on a determination of cacheability.
We agree with appellant that Frink neither teaches nor would have suggested to one of ordinary
skill in the art “conditioning a cache line flush on a determination of cacheability.” The examiner’s
conclusion that Frink suggests such a teaching is completely without support in the record. For this
reason, the obviousness rejection of claims 1 through 9 is reversed.
DECISION
The decision of the examiner rejecting claims 1 through 9 under 35 U.S.C. § 103 is reversed.
REVERSED
KENNETH W. HAIRSTON )
Administrative Patent Judge )
)
)
) BOARD OF PATENT
JERRY SMITH )
Administrative Patent Judge ) APPEALS AND
)
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