Appeal No. 97-0614
Application No. 08/212,465
9. A random access memory comprising:
plural memory planes, each memory plane including:
N memory arrays;
N serial registers, each serial register coupled to a
memory array;
N block write control circuits, each block write control
circuit coupled to a memory array;
the random access memory further comprising:
a row address decoder, coupled to at least one of the
memory arrays;
a column address decoder arranged for both block
decoding and individual column decoding, the column address
decoder being coupled to at least one of the memory arrays;
an address bus connecting with all of the memory arrays;
a data bus connecting with all of the memory arrays; and
the plural memory planes, the address bus, and the data
bus are all fabricated on a single semiconductor substrate.
The reference relied upon by the examiner as evidence of
obviousness is:
Pinkham et al. (Pinkham) 4,807,189 Feb. 21,
1989
The appealed claims stand rejected as under 35 U.S.C. §
102(b) as being anticipated by Pinkham.
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