Appeal No. 97-0614
Application No. 08/212,465
The respective positions of the examiner and the
appellants with regard to the propriety of these rejections are
set forth in the final rejection (Paper No. 8), the examiner's
answer (Paper No. 11) and the appellants’ brief (Paper No. 10).
Appellants’ Invention
Appellants disclose a random access memory 100 having
plural memory planes MP0-MP3. Each memory plane includes plural
memory arrays MR00-MR03 having serial registers SR00-SR03, block
write control circuits BWC00-BWC03 and row address decoder 153
coupled to the memory arrays. The random access memory further
includes a column address decoder 58, an address bus 150, 155 and
a data bus DQ0-DQ-15 coupled to the memory arrays. The memory
planes, address bus and the data bus are all positioned on a
single semiconductor substrate.
The Prior Art
Pinkham discloses a random access memory having memory
arrays 2. Serial registers 8, block write control circuit 24, 30,
3
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