Appeal No. 95-2914 Page 2
Application No. 07/447,969
BACKGROUND
The appellants' invention relates to a method for
fabricating a programmable interconnect structure having a low
leakage current in the preprogrammed state of less than 10
nanoamperes at 5.5 volts via plasma enhanced chemical vapor
deposited amorphous silicon features located between and
contacting two separate conductors. An understanding of the
invention can be derived from a reading of exemplary claim 1,
which is reproduced below.
1. A method for fabricating a programmable interconnect
structure for an integrated circuit, comprising the steps of:
fabricating a first conductor;
fabricating an insulating layer overlaying said first
conductor;
fabricating an opening through said insulating layer at a
selected location and terminating said opening at a portion of
said first conductor;
depositing using plasma enhanced chemical vapor
deposition a film of amorphous silicon upon said insulating
layer and in said opening;
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Last modified: November 3, 2007