Appeal No. 95-4899
Application 08/131,029
This is an appeal from the final rejection of claims 14
and 23 through 30.
The disclosed invention relates to a buffer connected
between a cache memory and one or more mass storage devices.
Claim 14 is illustrative of the claimed invention, and it
reads as follows:
14. In a computer system including a main memory, a
central processing unit (CPU), a buffer, a cache memory and
one or more mass storage devices, said CPU, main memory and
said cache memory being connected to a common bus, said buffer
being connected between said cache memory and said one or more
mass storage devices, a method of transferring data requested
by said CPU between said one or more mass storage devices and
said main memory, the method comprising the steps of:
determining whether said requested data is within said
cache memory;
transferring a predetermined amount of said requested
data from said mass storage device to said buffer when said
requested data is not within said cache memory;
transferring a portion of said predetermined amount of
said requested data from said buffer to said cache memory
while said predetermined amount of said requested data is
being transferred from said mass storage device to said
buffer; and
transferring a predetermined portion of said requested
data from said cache memory to said main memory while said
predeter-mined amount of said requested data is being
transferred from said mass storage device to said buffer.
The references relied on by the examiner are:
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