Appeal No. 95-4899
Application 08/131,029
look to Harris for a teaching of a FIFO buffer to add to
Moreno. After all, Moreno never discusses a “peripheral data
flow problem” (Answer, page 4), and we are not aware of such a
problem in Moreno. Even if we assume for the sake of
argument that it would have been obvious to one of ordinary
skill in the art to add a FIFO in Moreno, we are not convinced
by the examiner’s conclusion (Answer, page 4) that “it would
have been manifestly obvious to . . . incorporate a FIFO
buffer in between the cache memory and the disk of Moreno’s
system” (emphasis added). Other than appellant’s disclosed
and claimed invention, nothing in the record would have
suggested such a specific location for the buffer.
In summary, the obviousness rejection of claims 14, 23
through 25 and 27 through 30 is reversed because “nothing in
the prior art of record suggests incorporating a buffer
between a mass storage device and a cache memory” (Brief, page
15).
Ryan discloses a dual or two-part cache memory (Figure
2). A first cache memory 20 handles instruction data, and a
second cache memory 22 handles operand data. The data flow
through one cache memory is independent of the data flow
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