Appeal No. 95-4899
Application 08/131,029
disclosed nor claimed by appellant (Brief, pages 7 through 14;
Reply Brief, pages 4 through 11).
Appellant’s acknowledged prior art (specification, page
2) notes that it is well known in the art to use a cache
memory between a mass-storage device and a computer because of
the differences in processing speeds between the mass-storage
device and the computer. Moreno discloses (Figure 1) such a
cache memory 30 between a mass-storage device 26 and a host
computer 10.
The examiner acknowledges that Moreno discloses only a
single cache between the mass-storage device and the host
computer, and concludes that Moreno does not need a second one
because “[i]t appears that a single cache buffer is sufficient
to eliminate data flow problem in Moreno’s system” (Answer,
page 4).
Harris discloses the use of a first in-first out (FIFO)
buffer memory 7 for feeding data to a peripheral device (e.g.,
printer 6) that processes the data at a much slower rate than
the input rate of an input character source 1.
If the data flow problem in Moreno has been taken care of
by the cache memory (Answer, page 4), then we see no need to
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