Appeal No. 96-0908
Application 08/160,118
art. As discussed with respect to the rejection of claims 10
and 22, it would have been obvious to one having ordinary
skill in this art to make the register pair conditional store
instruction of Diefendorff dependent on different status bits.
Appellants' argument that "Diefendorff et al fails [sic] to
teach or suggest that his pixel merge instruction may be
conditioned upon any two of these four named type of status
bits as claimed" (Br23) fails to account for the knowledge of
those skilled in the art. The rejections of claims 41 and 43
over Auslander and Diefendorff and Kawata and Diefendorff are
sustained.
(11) Claims 11 and 23
(12) Claims 12 and 24
Claims 11 and 23 recite the operation of a "register pair
conditional write instruction" which conditionally supplies
the content of one of two registers to the first input of the
ALU based upon the state of a status bit.
Appellants state that "[t]he rejection has pointed out no
part of Auslander et al or Diefendorff et al that makes
obvious selection of the input to an arithmetic logic unit
from between two registers based upon a status bit" (Br12).
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