Appeal No. 96-0908
Application 08/160,118
change" (Br10). A similar argument is made with respect to
the combination of Kawata and Diefendorff (Br20).
The examiner notes that the instruction operation in
Auslander "sets one or more condition bits but not all
condition bits" (EA11) and "[t]hus, the unaffected bits are
deemed to be protected" (EA11). This does not address why one
of ordinary skill in the art of instruction set design would
have been motivated to provide masking bits in the instruction
as claimed. The examiner could have provided examples of
other instructions that had masking bits, but has not done so.
Auslander discloses that certain instructions set some status
bits, but leave others unchanged; e.g., the Divide Step (DVS)
instruction changes the Carry (CA) and Overflow (OV) condition
bits, but other condition bits are unchanged (col. 13,
lines 6-11). The unchanged bits might be considered to be
"protected." However, Auslander says nothing about the
instruction including bits indicating which bits are to be
protected. Kawata discloses only a sign status bit and does
not describe changing only some status bits. The examiner has
failed to establish a prima facie case of obviousness. The
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