Appeal No. 96-0908
Application 08/160,118
The examiner states that the claims do not require direct
storing of selected bits to memory because the claims do not
preclude additional intervening steps (EA7). It is true that
claim 1's recitation of "said instruction logic circuit
controlling said addressing circuit and said data circuit to
store said predetermined number of data bits stored in a first
data register into a specified address in said memory if a
status bit . . . has a first state" does not exclude an
intermediate step of storing the contents of the first
register in another register. However, because the store must
be "in response to a register pair conditional store
instruction," which limitation the examiner apparently
overlooks, the store must be performed with one instruction.
Storing in an intermediate register requires an additional
STORE instruction to move the results to memory (Diefendorff,
col. 11, lines 22-26). We agree with the examiner's reasoning
that one of ordinary skill in the art would have recognized
that if the whole register was stored the pixel merge
operation would be eliminated and the result could be sent
directly to memory (EA7), but it is not necessary to rely on
this reasoning since Diefendorff expressly discloses a direct
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